Alif Semiconductor /AE722F80F55D5AS_CM55_HE_View /ETH /ETH_MAC_INTERRUPT_STATUS

PHY Interrupt This bit is set when rising edge is detected on the ETH_IRQ input. This bit is cleared when this register is read (or this bit is written to 1 when the ETH_MAC_CSR_SW_CTRL[RCWE] bit is set).

0 (Val_0x0): PHY interrupt not detected

1 (Val_0x1): PHY interrupt detected

PMT Interrupt Status This bit is set when a Magic packet or Wake-on-LAN packet is received in the power-down mode (the ETH_MAC_PMT_CONTROL_STATUS[RWKPRCVD] and ETH_MAC_PMT_CONTROL_STATUS[MGKPRCVD] bits). This bit is cleared when corresponding interrupt source bit are cleared because of a Read operation to the ETH_MAC_PMT_CONTROL_STATUS register (or corresponding interrupt source bit of ETH_MAC_PMT_CONTROL_STATUS register is written to 1 when the ETH_MAC_CSR_SW_CTRL[RCWE] bit is set).

0 (Val_0x0): PMT interrupt status not active

1 (Val_0x1): PMT interrupt status active

Timestamp Interrupt Status This bit is set when any of the following conditions is true:

• The ETH_MAC_TIMESTAMP_STATUS[TSTRGTERR0] bit is set.
• The ETH_MAC_TIMESTAMP_STATUS[TSTARGT0] bit is set.
• The ETH_MAC_TIMESTAMP_STATUS[TSSOVF] bit is set.
• When drop transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in the ETH_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS and ETH_MAC_TX_TIMESTAMP_STATUS_SECONDS registers. This bit is cleared when the corresponding interrupt source bit is read in the ETH_MAC_TIMESTAMP_STATUS register or the corresponding interrupt source bit is written to 1 when the ETH_MAC_CSR_SW_CTRL[RCWE] bit is set.

0 (Val_0x0): Timestamp interrupt status not active

1 (Val_0x1): Timestamp interrupt status active

Transmit Status Interrupt This bit indicates the status of transmitted packets. This bit is set when any of the following bits is set:

• ETH_MAC_RX_TX_STATUS[EXCOL]
• ETH_MAC_RX_TX_STATUS[LCOL]
• ETH_MAC_RX_TX_STATUS[EXDEF]
• ETH_MAC_RX_TX_STATUS[LCARR]
• ETH_MAC_RX_TX_STATUS[NCARR]
• ETH_MAC_RX_TX_STATUS[TJT]

0 (Val_0x0): Transmit interrupt status not active

1 (Val_0x1): Transmit interrupt status active

Receive Status Interrupt This bit indicates the status of received packets. This bit is set when the RWT bit is set in the ETH_MAC_RX_TX_STATUS register. This bit is cleared when the corresponding interrupt source bit is read (or corresponding interrupt source bit is written to 1 when the ETH_MAC_CSR_SW_CTRL[RCWE] bit is set) in the ETH_MAC_RX_TX_STATUS register.

0 (Val_0x0): Receive interrupt status not active

1 (Val_0x1): Receive interrupt status active

MDIO Interrupt Status This bit indicates an interrupt event after the completion of MDIO operation. To reset this bit, the application has to read this bit/Write 1 to this bit when the ETH_MAC_CSR_SW_CTRL[RCWE] bit is set. Access restriction applies. Clears on read (or write of 1 when the ETH_MAC_CSR_SW_CTRL[RCWE] bit is set). Self-set to 1 on internal event.

0 (Val_0x0): MDIO interrupt status not active

1 (Val_0x1): MDIO interrupt status active